Gate arrays comprise many identical base cells arranged in rows and columns. Metallization patterns are fabricated on the base cells of a gate array to create an application specific integrated circuit (ASIC). Gate arrays are thus configurable to implement various logic circuits based on customer specifications.
Conventional base cells for gate arrays of application specific integrated circuit (ASIC) chips are generally tiled laterally. Figure 1 illustrates a plan view of a representative portion of the tiling of prior art bipolar/complementary metal oxide semiconductor (BiCMOS) base cells. Complementary metal oxide semiconductor (CMOS) sites, which primarily include CMOS circuitry, are designated by the letter C. Bipolar sites, which primarily include bipolar drive circuitry, are designated by the letter B. The connectivity between sites is generally lateral, as indicated by connection symbol 2.
Note that although the lateral connectivity between abutting CMOS sites generally present no problems, the lateral connection of CMOS sites across a bipolar site effectively precludes the use of the bipolar site interposed therebetween. The interconnect metallization between such CMOS sites will not allow use of the interposed bipolar site because there is not enough area left to make physical connection to the bipolar device. This type of preclusion of bipolar sites can lead to significant under utilization of gate array chip real estate. An improved base cell tiling is desired which includes improved bipolar site utilization. Further, high input capacitances due to architectural constraints and unused cell site areas lead to less than optimal gate array operation speed.